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| ? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor technical data this document contains de tailed information on power considerations, ac/dc electrical characteristics, and ac timing specifications for revision a,b, and c of the mpc850 family. 1overview the mpc850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller appli cations, excelling particularly in communications and networking products. the mpc850, which includes support for ethern et, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. it is provides functions similar to the mpc860, with system enhancements such as universal serial bus (usb) support and a larger (8-kbyte) dual-port ram. in addition to a high-performance embedded mpc8xx core, the mpc850 integrates system functions, such as a versatile memory controller and a communications processor module (cpm) that incorporates a specialized, independent risc communications processor (referred to as the cp). this separate processor off-loads peripheral tasks from the embedded mpc8xx core. document number: mpc850ec rev. 2, 07/2005 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. electrical and thermal characteristics . . . . . . . . . . . . 7 4. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 5. power considerations . . . . . . . . . . . . . . . . . . . . . . . . . 9 6. bus signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7. ieee 1149.1 electrical specifications . . . . . . . . . . . 39 8. cpm electrical characteristics . . . . . . . . . . . . . . . . . 41 9. mechanical data and ordering information . . . . . . . 63 10. document revision history . . . . . . . . . . . . . . . . . . . 68 mpc850 powerquicc? integrated communications processor hardware specifications
mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 2 freescale semiconductor overview the cpm of the mpc850 supports up to seven serial channels, as follows: ? one or two serial communications controlle rs (sccs). the sccs support ethernet, atm (mpc850sr and mpc850dsl), hdlc and a number of other protocols, along with a transparent mode of operation. one usb channel two serial management controllers (smcs) one i 2 c port one serial peripheral interface (spi). table 1 shows the functionality supported by the members of the mpc850 family. additional documentation may be provided for parts listed in table 1 . table 1. mpc850 functionality matrix part number of sccs supported ethernet support atm support usb support multi-channel hdlc support number of pcmcia slots supported mpc850 1 yes - yes - 1 mpc850de 2 yes - yes - 1 mpc850sr 2 yes yes yes yes 1 mpc850dsl 2 yes yes yes no 1 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 3 features 2features figure 1 is a block diagram of the mpc850, showing its major components and the relationships among those components: figure 1. mpc850 microprocessor block diagram the following list summarizes the main features of the mpc850: embedded single-issue, 32-bit mpc8xx core (implementing the powerpc architecture) with thirty-two 32-bit general-purpose registers (gprs) ? performs branch folding and branch prediction with conditional prefetch, but without conditional execution system interface unit memory controller bus interface unit system functions real-time clock pcmcia interface bus embedded 2-kbyte i-cache mmu 1-kbyte d-cache data mmu load/store instruction bus parallel i/o baud rate generators dual-port ram interrupt controller four timers 20 virtual 2 virtual 32-bit risc communications processor (cp) and program rom scc2 usb spi timer non-multiplexed serial interface mpc8xx core instruction idma channels serial dma and channels unified bus communications processor module peripheral bus scc3 i 2 c ? utopia ports (850sr & dsl) smc1 smc2 time slot assigner tdma mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 4 freescale semiconductor features ? 2-kbyte instruction cache and 1-kbyte data cache (harvard architecture) ? caches are two-way, set-associative ? physically addressed ? cache blocks can be updated with a 4-word line burst ? least-recently used (lru) replacement algorithm ? lockable one-line granularity ? memory management units (mmus) with 8-entr y translation lookaside buffers (tlbs) and fully-associative instruction and data tlbs ? mmus support multiple page sizes of 4 kbytes, 16 kbytes, 256 kbytes, 512 kbytes, and 8 mbytes; 16 virtual address spaces and eight protection groups advanced on-chip emulation debug mode data bus dynamic bus sizing for 8, 16, and 32-bit buses ? supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian memory systems ? twenty-six external address lines completely static design (0?80 mhz operation) system integration unit (siu) ? hardware bus monitor ? spurious interrupt monitor ? software watchdog ? periodic interrupt timer ? low-power stop mode ? clock synthesizer ? decrementer, time base, and real-time clock (rtc) from the powerpc architecture ? reset controller ? ieee 1149.1 test access port (jtag) memory controller (eight banks) ? glueless interface to dram single in-line memory modules (simms), synchronous dram (sdram), static random-access memory (sram), electrically programmable read-only memory (eprom), flash eprom, etc. ? memory controller programmable to support most size and speed memory interfaces ? boot chip-select available at reset (options for 8, 16, or 32-bit memory) ? variable block sizes, 32 kbytes to 256 mbytes ? selectable write protection ? on-chip bus arbiter supports one external bus master ? special features for burst mode support general-purpose timers ? four 16-bit timers or two 32-bit timers mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 5 features ? gate mode can enable/disable counting ? interrupt can be masked on reference match and event capture interrupts ? eight external interrupt request (irq) lines ? twelve port pins with interrupt capability ? fifteen internal interrupt sources ? programmable priority among sccs and usb ? programmable highest-priority request single socket pcmcia-ata interface ? master (socket) interface, release 2.1 compliant ? single pcmcia socket ? supports eight memory or i/o windows communications processor module (cpm) ? 32-bit, harvard architecture, scalar risc communications processor (cp) ? protocol-specific command sets (for example, graceful stop transmit stops transmission after the current frame is finished or immediately if no frame is being sent and close rxbd closes the receive buffer descriptor) ? supports continuous mode transmission and reception on all serial channels ? up to 8 kbytes of dual-port ram ? twenty serial dma (sdma) channels for the seri al controllers, including eight for the four usb endpoints ? three parallel i/o registers with open-drain capability four independent baud-ra te generators (brgs) ? can be connected to any scc, smc, or usb ? allow changes during operation ? autobaud support option two sccs (serial communications controllers) ? ethernet/ieee 802.3, supporting full 10-mbps operation ? hdlc/sdlc? (all channels supported at 2 mbps) ? hdlc bus (implements an hdlc-based local area network (lan)) ? asynchronous hdlc to support ppp (point-to-point protocol) ? appletalk ? ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? serial infrared (irda) ? totally transparent (bit streams) ? totally transparent (frame based with optional cyclic redundancy check (crc)) mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 6 freescale semiconductor features quicc multichannel controller (qmc) microcode features ? up to 64 independent communication channels on a single scc ? arbitrary mapping of 0?31 channels to any of 0?31 tdm time slots ? supports either transparent or hdlc protocols for each channel ? independent txbds/rx and event/interrupt reporting for each channel one universal serial bus controller (usb) ? supports host controller and slave modes at 1.5 mbps and 12 mbps two serial management controllers (smcs) ? uart ? transparent ? general circuit interface (gci) controller ? can be connected to the time-division-multiplexed (tdm) channel one serial peripheral interface (spi) ? supports master and slave modes ? supports multimaster operation on the same bus one i 2 c ? (interprocessor-integrated circuit) port ? supports master and slave modes ? supports multimaster environment time slot assigner ? allows sccs and smcs to run in multiplexed operation ? supports t1, cept, pcm highway, isdn basic rate, isdn primary rate, user-defined ? 1- or 8-bit resolution ? allows independent transmit and rece ive routing, frame syncs, clocking ? allows dynamic changes ? can be internally connected to four se rial channels (two sccs and two smcs) low-power support ? full high: all units fully powered at high clock frequency ? full low: all units fully powered at low clock frequency ? doze: core functional units disabled except time base, decrementer, pll, memory controller, real-time clock, and cpm in low-power standby ? sleep: all units disabled except real-time clock and periodic interrupt timer. pll is active for fast wake-up ? deep sleep: all units disabled including pll, except the real-time clock and periodic interrupt timer ? low-power stop: to provide lower power dissipation mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 7 electrical and thermal characteristics ? separate power supply input to operate internal logic at 2.2 v when operating at or below 25 mhz ? can be dynamically shifted betw een high frequency (3.3 v internal) and low frequency (2.2 v internal) operation debug interface ? eight comparators: four operate on instruction address, two operate on data address, and two operate on data ? the mpc850 can compare using the =, , <, and > conditions to generate watchpoints ? each watchpoint can genera te a breakpoint internally 3.3-v operation with 5-v ttl compatibility on all general purpose i/o pins. 3 electrical and thermal characteristics this section provides the ac and dc electrical specifi cations and thermal characteristics for the mpc850. table 2 provides the maximum ratings. this device contains circuitry protecting against dama ge due to high-static voltage or electrical fields; however, it is advised that normal precautions be take n to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circ uit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic vo ltage level (for example, either gnd or v cc ). table 3 provides the package thermal characteristics for the mpc850. table 2. maximum ratings (gnd = 0v) rating symbol value unit supply voltage vddh -0.3 to 4.0 v vddl -0.3 to 4.0 v kapwr -0.3 to 4.0 v vddsyn -0.3 to 4.0 v input voltage 1 1 functional operating conditions are provided with the dc electrical specifications in table 5 . absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. caution: all inputs that tolerate 5 v cannot be more than 2.5 v greater than the supply voltage. this restriction applies to power-up and normal operation (that is, if the mpc850 is unpowered, voltage greater than 2.5 v must not be applied to its inputs). v in gnd-0.3 to vddh + 2.5 v v junction temperature 2 2 the mpc850, a high-frequency device in a bga package, does not provide a guaranteed maximum ambient temperature. only maximum junction temperature is guaranteed. it is the responsib ility of the user to consider power dissipation and thermal management. junction temperature ratings are the same regardless of frequency rating of the device. t j 0 to 95 (standard) -40 to 95 (extended) c storage temperature range t stg -55 to +150 c mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 8 freescale semiconductor thermal characteristics 4 thermal characteristics table 3 shows the thermal characteristics for the mpc850. table 4 provides power dissipation information. table 5 provides the dc electrical characteristics for the mpc850. table 3. thermal characteristics characteristic symbol value unit thermal resistance for bga 1 1 for more information on the design of thermal vias on multilayer boards and bga layout considerations in general, refer to an-1231/d, plastic ball grid array application note available from your local freescale sales office. ja 40 2 2 assumes natural convection and a single layer board (no thermal vias). c/w ja 31 3 3 assumes natural convection, a multilayer board with thermal vias 4 , 1 watt mpc850 dissipation, and a board temperature rise of 20 c above ambient. c/w ja 24 4 4 assumes natural convection, a multilayer board with thermal vias 4 , 1 watt mpc850 dissipation, and a board temperature rise of 13 c above ambient. t j = t a + (p d ja ) p d = (v dd i dd ) + p i/o where: p i/o is the power dissipation on pins c/w thermal resistance for bga (junction-to-case) jc 8 c/w table 4. power dissipation (p d ) characteristic frequency (mhz) typical 1 1 typical power dissipation is measured at 3.3v maximum 2 2 maximum power dissipation is measured at 3.65 v unit power dissipation all revisions (1:1) mode 33 tbd 515 mw 40 tbd 590 mw 50 tbd 725 mw table 5. dc electrical specifications characteristic symbol min max unit operating voltage at 40 mhz or less vddh, vddl, kapwr, vddsyn 3.0 3.6 v operating voltage at 40 mhz or higher vddh, vddl, kapwr, vddsyn 3.135 3.465 v input high voltage (address bus, data bus, extal, extclk, and all bus control/status signals) vih 2.0 3.6 v input high voltage (all general purpose i/o and peripheral pins) vih 2.0 5.5 v mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 9 power considerations 5 power considerations the average chip-junction temperature , t j , in c can be obtained from the equation: t j = t a + (p d ja )(1) where t a = ambient temperature , c input low voltage vil gnd 0.8 v extal, extclk input high voltage vihc 0.7*(vcc) vcc+0.3 v input leakage current, vin = 5.5 v (except tms, trst , dsck and dsdi pins) i in ? 100 a input leakage current, vin = 3.6v (except tms, trst , dsck and dsdi pins) i in ?10a input leakage current, vin = 0v (except tms, trst , dsck and dsdi pins) i in ?10a input capacitance c in ?20pf output high voltage, ioh = -2.0 ma, vddh = 3.0v except xtal, xfc, and open-drain pins voh 2.4 ? v output low voltage clkout 3 iol = 3.2 ma 1 iol = 5.3 ma 2 iol = 7.0 ma pa[14]/usboe , pa[12]/txd2 iol = 8.9 ma ts , ta , tea , bi , bb , hreset , sreset vol ? 0.5 v 1 a[6:31], tsiz0/reg , tsiz1, d[0:31], dp[0:3]/irq[3:6] , rd/wr , burst , rsv /irq2 , ip_b[0:1]/iwp[0:1]/vfls[0:1], ip_b2/iois16_b /at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/vf1, ip_b6/dsdi/at0, ip_b7/ptr /at3, pa[15]/usbrxd, pa[13]/rxd2, pa[9]/l1txda/smrxd2, pa[8]/l1rxda/smtxd2, pa[7]/clk1/tin1/l1rclka/brgo1, pa[6]/clk2/tout1 /tin3, pa[5]/clk3/tin2/l1tclka/brgo2, pa[4]/clk4/tout2 /tin4, pb[31]/spisel , pb[30]/spiclk/txd3, pb[29]/spimosi /rxd3, pb[28]/spimiso/brgo3, pb[27]/i2csda/brgo1, pb[26]/i2cscl/brgo2, pb[25]/smtxd1/txd3, pb[24]/smrxd1/rxd3, pb[23]/smsyn1 /sdack1 , pb[22]/smsyn2 /sdack2 , pb[19]/l1st1, pb[18]/rts2 /l1st2, pb[17]/l1st3, pb[16]/l1rqa /l1st4, pc[15]/dreq0 /l1st5, pc[14]/dreq1 /rts2 /l1st6, pc[13]/l1st7/rts3 , pc[12]/l1rqa /l1st8, pc[11]/usbrxp, pc[10]/tgate1 /usbrxn, pc[9]/cts2 , pc[8]/cd2 /tgate1 , pc[7]/usbtxp, pc[6]/usbtxn, pc[5]/cts3 /l1tsynca/sdack1 , pc[4]/cd3 /l1rsynca, pd[15], pd[14], pd[13], pd[12], pd[11], pd[10], pd[9], pd[8], pd[7], pd[6], pd[5], pd[4], pd[3] 2 bdip /gpl_b5 , br , bg , frz/irq6 , cs [0:5], cs6 /ce1_b , cs7 /ce2_b , we0 /bs_ab0 /iord , we1 /bs_ab1 /iowr , we2 /bs_ab2 /pcoe , we3 /bs_ab3 /pcwe , gpl_a0 /gpl_b0 , oe /gpl_a1 /gpl_b1 , gpl_a [2:3]/gpl_b [2:3]/cs [2:3], upwaita/gpl_a4 /as , upwaitb/gpl_b4 , gpl_a5 , ale_b/dsck/at1, op2/modck1/sts , op3/modck2/dsdo 3 the mpc850 ibis model must be used to accurately model the behavior of the clkout output driver for the full and half drive setting. due to the nature of the clkout output buffer, ioh and iol for clkout should be extracted from the ibis model at any output voltage level. table 5. dc electrical specifications (continued) characteristic symbol min max unit mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 10 freescale semiconductor bus signal timing ja = package thermal resistance , junction to ambient , c/w p d = p int + p i/o p int = i dd x v dd , watts?chip internal power p i/o = power dissipation on input and output pins?user determined for most applications p i/o < 0.3 p int and can be neglected. if p i/o is neglected , an approximate relationship between p d and t j is: p d = k (t j + 273 c)(2) solving equations (1) and (2) for k gives: k = p d (t a + 273 c) + ja p d 2 (3) where k is a constant pertaining to the particular pa rt. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 5.1 layout practices each v cc pin on the mpc850 should be provided with a low-impedance path to the board?s supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and gnd should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the mpc850 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data busses. maximum pc trace lengths of six inches are recommended. capacita nce calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb la yout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. 6 bus signal timing table 6 provides the bus operation timing for the mpc850 at 50 mhz, 66 mhz, and 80 mhz. timing information for other bus speeds can be inter polated by equation using the mpc850 electrical specifications spreadsheet found at http://www.mot.com/netcomm. the maximum bus speed supported by the mpc850 is 50 mhz. higher-speed parts must be operated in half-speed bus mode (for example, an mpc850 used at 66 mhz must be configured for a 33 mhz bus). the timing for the mpc850 bus shown assumes a 50-pf load. this timing can be derated by 1 ns per 10 pf. derating calculations can also be performed usi ng the mpc850 electrical specifications spreadsheet. mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 11 bus signal timing table 6. bus operation timing 1 num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max b1 clkout period 20 ? 30.30 ? 25 ? ? ? ns b1a extclk to clkout phase skew (extclk > 15 mhz and mf <= 2) -0.90 0.90 -0.90 0.90 -0.90 0.90 ? 50.00 ns b1b extclk to clkout phase skew (extclk > 10 mhz and mf < 10) -2.30 2.30 -2.30 2.30 -2.30 2.30 ? 50.00 ns b1c clkout phase jitter (extclk > 15 mhz and mf <= 2) 2 -0.60 0.60 -0.60 0.60 -0.60 0.60 ? 50.00 ns b1d clkout phase jitter 2 -2.00 2.00 -2.00 2.00 -2.00 2.00 ? 50.00 ns b1e clkout frequency jitter (mf < 10) 2 ? 0.50 ? 0.50 ? 0.50 ? 50.00 % b1f clkout frequency jitter (10 < mf < 500) 2 ? 2.00 ? 2.00 ? 2.00 ? 50.00 % b1g clkout frequency jitter (mf > 500) 2 ? 3.00 ? 3.00 ? 3.00 ? 50.00 % b1h frequency jitter on extclk 3 ? 0.50 ? 0.50 ? 0.50 ? 50.00 % b2 clkout pulse width low 8.00 ? 12.12 ? 10.00 ? ? 50.00 ns b3 clkout width high 8.00 ? 12.12 ? 10.00 ? ? 50.00 ns b4 clkout rise time ? 4.00 ? 4.00 ? 4.00 ? 50.00 ns b5 clkout fall time ? 4.00 ? 4.00 ? 4.00 ? 50.00 ns b7 clkout to a[6?31], rd/wr , burst , d[0?31], dp[0?3] invalid 5.00 ? 7.58 ? 6.25 ? 0.250 50.00 ns b7a clkout to tsiz[0?1], reg , rsv , at[0?3], bdip , ptr invalid 5.00 ? 7.58 ? 6.25 ? 0.250 50.00 ns b7b clkout to br , bg , frz, vfls[0?1], vf[0?2] iwp[0?2], lwp[0?1], sts invalid 4 5.00 ? 7.58 ? 6.25 ? 0.250 50.00 ns b8 clkout to a[6?31], rd/wr , burst , d[0?31], dp[0?3] valid 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns b8a clkout to tsiz[0?1], reg , rsv , at[0?3] bdip , ptr valid 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns b8b clkout to br , bg , vfls[0?1], vf[0?2], iwp[0?2], frz, lwp[0?1], sts valid 4 5.00 11.74 7.58 14.33 6.25 13.00 0.250 50.00 ns mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 12 freescale semiconductor bus signal timing b9 clkout to a[6?31] rd/wr , burst , d[0?31], dp[0?3], tsiz[0?1], reg , rsv , at[0?3], ptr high-z 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns b11 clkout to ts , bb assertion 5.00 11.00 7.58 13.58 6.25 12.25 0.250 50.00 ns b11a clkout to ta , bi assertion, (when driven by the memory controller or pcmcia interface) 2.50 9.25 2.50 9.25 2.50 9.25 ? 50.00 ns b12 clkout to ts , bb negation 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns b12a clkout to ta , bi negation (when driven by the memory controller or pcmcia interface) 2.50 11.00 2.50 11.00 2.50 11.00 ? 50.00 ns b13 clkout to ts , bb high-z 5.00 19.00 7.58 21.58 6.25 20.25 0.250 50.00 ns b13a clkout to ta , bi high-z, (when driven by the memory controller or pcmcia interface) 2.50 15.00 2.50 15.00 2.50 15.00 ? 50.00 ns b14 clkout to tea assertion 2.50 10.00 2.50 10.00 2.50 10.00 ? 50.00 ns b15 clkout to tea high-z 2.50 15.00 2.50 15.00 2.50 15.00 ? 50.00 ns b16 ta , bi valid to clkout(setup time) 5 9.75 ? 9.75 ? 9.75 ? ? 50.00 ns b16a tea , kr , retry , valid to clkout (setup time ) 5 10.00 ? 10.00 ? 10.00 ? ? 50.00 ns b16b bb , bg , br valid to clkout (setup time) 6 8.50 ? 8.50 ? 8.50 ? ? 50.00 ns b17 clkout to ta , tea , bi , bb , bg , br valid (hold time). 5 1.00 ? 1.00 ? 1.00 ? ? 50.00 ns b17a clkout to kr , retry , except tea valid (hold time) 2.00 ? 2.00 ? 2.00 ? ? 50.00 ns b18 d[0?31], dp[0?3] valid to clkout rising edge (setup time) 7 6.00 ? 6.00 ? 6.00 ? ? 50.00 ns b19 clkout rising edge to d[0?31], dp[0?3] valid (hold time) 7 1.00 ? 1.00 ? 1.00 ? ? 50.00 ns b20 d[0?31], dp[0?3] valid to clkout falling edge (setup time) 8 4.00 ? 4.00 ? 4.00 ? ? 50.00 ns b21 clkout falling edge to d[0?31], dp[0?3] valid (hold time) 8 2.00 ? 2.00 ? 2.00 ? ? ? ? table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 13 bus signal timing b22 clkout rising edge to cs asserted gpcm acs = 00 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns b22a clkout falling edge to cs asserted gpcm acs = 10, trlx = 0,1 ? 8.00 ? 8.00 ? 8.00 ? 50.00 ns b22b clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 0 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns b22c clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 1 7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns b23 clkout rising edge to cs negated gpcm read access, gpcm write access acs = 00, trlx = 0 & csnt = 0 2.00 8.00 2.00 8.00 2.00 8.00 ? 50.00 ns b24 a[6?31] to cs asserted gpcm acs = 10, trlx = 0. 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b24a a[6?31] to cs asserted gpcm acs = 11, trlx = 0 8.00 ? 13.00 ? 11.00 ? 0.500 50.00 ns b25 clkout rising edge to oe , we[0?3] asserted ? 9.00 ? 9.00 ? 9.00 ? 50.00 ns b26 clkout rising edge to oe negated 2.00 9.00 2.00 9.00 2.00 9.00 ? 50.00 ns b27 a[6?31] to cs asserted gpcm acs = 10, trlx = 1 23.00 ? 36.00 ? 29.00 ? 1.250 50.00 ns b27a a[6?31] to cs asserted gpcm acs = 11, trlx = 1 28.00 ? 43.00 ? 36.00 ? 1.500 50.00 ns b28 clkout rising edge to we[0?3] negated gpcm write access csnt = 0 ? 9.00 ? 9.00 ? 9.00 ? 50.00 ns b28a clkout falling edge to we[0?3] negated gpcm write access trlx = 0,1 csnt = 1, ebdf = 0 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns b28b clkout falling edge to cs negated gpcm write access trlx = 0,1 csnt = 1, acs = 10 or acs = 11, ebdf = 0 ? 12.00 ? 14.00 ? 13.00 0.250 50.00 ns table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 14 freescale semiconductor bus signal timing b28c clkout falling edge to we[0?3] negated gpcm write access trlx = 0,1 csnt = 1 write access trlx = 0, csnt = 1, ebdf = 1 7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns b28d clkout falling edge to cs negated gpcm write access trlx = 0,1 csnt = 1, acs = 10 or acs = 11, ebdf = 1 ? 14.00 ? 18.00 ? 16.00 0.375 50.00 ns b29 we[0?3] negated to d[0?31], dp[0?3] high-z gpcm write access, csnt = 0 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b29a we[0?3] negated to d[0?31], dp[0?3] high-z gpcm write access, trlx = 0 csnt = 1, ebdf = 0 8.00 ? 13.00 ? 11.00 ? 0.500 50.00 ns b29b cs negated to d[0?31], dp[0?3], high-z gpcm write access, acs = 00, trlx = 0 & csnt = 0 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b29c cs negated to d[0?31], dp[0?3] high-z gpcm write access, trlx = 0, csnt = 1, acs = 10 or acs = 11, ebdf = 0 8.00 ? 13.00 ? 11.00 ? 0.500 50.00 ns b29d we[0?3] negated to d[0?31], dp[0?3] high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 0 28.00 ? 43.00 ? 36.00 ? 1.500 50.00 ns b29e cs negated to d[0?31], dp[0?3] high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 0 28.00 ? 43.00 ? 36.00 ? 1.500 50.00 ns b29f we[0?3] negated to d[0?31], dp[0?3] high-z gpcm write access trlx = 0, csnt = 1, ebdf = 1 5.00 ? 9.00 ? 7.00 ? 0.375 50.00 ns b29g cs negated to d[0?31], dp[0?3] high-z gpcm write access trlx = 0, csnt = 1, acs = 10 or acs = 11, ebdf = 1 5.00 ? 9.00 ? 7.00 ? 0.375 50.00 ns table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 15 bus signal timing b29h we[0?3] negated to d[0?31], dp[0?3] high-z gpcm write access trlx = 0, csnt = 1, ebdf = 1 25.00 ? 39.00 ? 31.00 ? 1.375 50.00 ns b29i cs negated to d[0?31], dp[0?3] high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 1 25.00 ? 39.00 ? 31.00 ? 1.375 50.00 ns b30 cs , we[0?3] negated to a[6?31] invalid gpcm write access 9 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b30a we[0?3] negated to a[6?31] invalid gpcm write access, trlx = 0, csnt = 1, cs negated to a[6?31] invalid gpcm write access trlx = 0, csnt =1, acs = 10 or acs = 11, ebdf = 0 8.00 ? 13.00 ? 11.00 ? 0.500 50.00 ns b30b we[0?3] negated to a[6?31] invalid gpcm write access, trlx = 1, csnt = 1. cs negated to a[6?31] invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 0 28.00 ? 43.00 ? 36.00 ? 1.500 50.00 ns b30c we[0?3] negated to a[6?31] invalid gpcm write access, trlx = 0, csnt = 1. cs negated to a[6?31] invalid gpcm write access, trlx = 0, csnt = 1, acs = 10 or acs = 11, ebdf = 1 5.00 ? 8.00 ? 6.00 ? 0.375 50.00 ns b30d we[0?3] negated to a[6?31] invalid gpcm write access trlx = 1, csnt =1, cs negated to a[6?31] invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 1 25.00 ? 39.00 ? 31.00 ? 1.375 50.00 ns table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 16 freescale semiconductor bus signal timing b31 clkout falling edge to cs valid - as requested by control bit cst4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 1.50 6.00 ? 50.00 ns b31a clkout falling edge to cs valid - as requested by control bit cst1 in the corresponding word in the upm 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns b31b clkout rising edge to cs valid - as requested by control bit cst2 in the corresponding word in the upm 1.50 8.00 1.50 8.00 1.50 8.00 ? 50.00 ns b31c clkout rising edge to cs valid - as requested by control bit cst3 in the corresponding word in the upm 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns b31d clkout falling edge to cs valid - as requested by control bit cst1 in the corresponding word in the upm ebdf = 1 9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns b32 clkout falling edge to bs valid - as requested by control bit bst4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 1.50 6.00 ? 50.00 ns b32a clkout falling edge to bs valid - as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns b32b clkout rising edge to bs valid - as requested by control bit bst2 in the corresponding word in the upm 1.50 8.00 1.50 8.00 1.50 8.00 ? 50.00 ns b32c clkout rising edge to bs valid - as requested by control bit bst3 in the corresponding word in the upm 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns b32d clkout falling edge to bs valid - as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns b33 clkout falling edge to gpl valid - as requested by control bit gxt4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 1.50 6.00 ? 50.00 ns table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 17 bus signal timing b33a clkout rising edge to gpl valid - as requested by control bit gxt3 in the corresponding word in the upm 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns b34 a[6?31] and d[0?31] to cs valid - as requested by control bit cst4 in the corresponding word in the upm 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b34a a[6?31] and d[0?31] to cs valid - as requested by control bit cst1 in the corresponding word in the upm 8.00 ? 13.00 ? 11.00 ? 0.500 50.00 ns b34b a[6?31] and d[0?31] to cs valid - as requested by cst2 in the corresponding word in upm 13.00 ? 21.00 ? 17.00 ? 0.750 50.00 ns b35 a[6?31] to cs valid - as requested by control bit bst4 in the corresponding word in upm 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b35a a[6?31] and d[0?31] to bs valid - as requested by bst1 in the corresponding word in the upm 8.00 ? 13.00 ? 11.00 ? 0.500 50.00 ns b35b a[6?31] and d[0?31] to bs valid - as requested by control bit bst2 in the corresponding word in the upm 13.00 ? 21.00 ? 17.00 ? 0.750 50.00 ns b36 a[6?31] and d[0?31] to gpl valid - as requested by control bit gxt4 in the corresponding word in the upm 3.00 ? 6.00 ? 4.00 ? 0.250 50.00 ns b37 upwait valid to clkout falling edge 10 6.00 ? 6.00 ? 6.00 ? ? 50.00 ns b38 clkout falling edge to upwait valid 10 1.00 ? 1.00 ? 1.00 ? ? 50.00 ns b39 as valid to clkout rising edge 11 7.00 ? 7.00 ? 7.00 ? ? 50.00 ns b40 a[6?31], tsiz[0?1], rd/wr , burst , valid to clkout rising edge. 7.00 ? 7.00 ? 7.00 ? ? 50.00 ns b41 ts valid to clkout rising edge (setup time) 7.00 ? 7.00 ? 7.00 ? ? 50.00 ns table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 18 freescale semiconductor bus signal timing b42 clkout rising edge to ts valid (hold time) 2.00 ? 2.00 ? 2.00 ? ? 50.00 ns b43 as negation to memory controller signals negation ?tbd?tbdtbd? ? 50.00 ns 1 the minima provided assume a 0 pf load, whereas maxima assume a 50pf load. for frequencies not marked on the part, new bus timing must be calculated for all frequency-dependent ac parameters. frequency-dependent ac parameters are those with an entry in the ffactor column. ac parameters without an ffactor entry do not need to be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part. the following equations should be used in these calculations. for a frequency f, the following equations should be applied to each one of the above parameters: for minima: for maxima: where: d is the parameter value to the frequency required in ns f is the operation frequency in mhz d 50 is the parameter value defined for 50 mhz cap load is the capacitance load on the signal in question. ffactor is the one defined for each of the parameters in the table. 2 phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value. 3 if the rate of change of the frequency of extal is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the maximum allowed jitter on extal can be up to 2%. 4 the timing for br output is relevant when the mpc850 is selected to work with external bus arbiter. the timing for bg output is relevant when the mpc850 is selected to work with internal bus arbiter. 5 the setup times required for ta , tea , and bi are relevant only when they are supplied by an external device (and not when the memory controller or the pcmcia interface drives them). 6 the timing required for br input is relevant when the mpc850 is selected to work with the internal bus arbiter. the timing for bg input is relevant when the mpc850 is selected to work with the external bus arbiter. 7 the d[0?31] and dp[0?3] input timings b20 and b21 refer to the rising edge of the clkout in which the ta input signal is asserted. 8 the d[0:31] and dp[0:3] input timings b20 and b21 refer to the falling edge of clkout. this timing is valid only for read accesses controlled by chip-selects controlled by the upm in the memory controller, for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout. 9 the timing b30 refers to cs when acs = '00' and to we[0:3] when csnt = '0'. 10 the signal upwait is considered asynchronous to clkout and synchronized internally. the timings specified in b37 and b38 are specified to enable the freeze of the upm output signals. 11 the as signal is considered asynchronous to clkout. table 6. bus operation timing 1 (continued) num characteristic 50 mhz 66 mhz 80 mhz ffact cap load (default 50 pf) unit min max min max min max d = ffactor x 1000 f (d 50 - 20 x ffactor) + d = ffactor x 1000 f (d 50 -20 x ffactor) ++ 1ns(cap load - 50) / 10 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 19 bus signal timing figure 2 is the control timing diagram. figure 2. control timing figure 3 provides the timing for the external clock. figure 3. external clock timing clkout outputs a b 2.0 v 0.8 v 0.8 v 2.0 v 2.0 v 0.8 v 2.0 v 0.8 v outputs 2.0 v 0.8 v 2.0 v 0.8 v b a inputs 2.0 v 0.8 v 2.0 v 0.8 v d c inputs 2.0 v 0.8 v 2.0 v 0.8 v c d a maximum output delay specification b minimum output hold time c minimum input setup time specification d minimum input hold time specification clkout b1 b5 b3 b4 b1 b2 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 20 freescale semiconductor bus signal timing figure 4 provides the timing for the synchronous output signals. figure 4. synchronous output signals timing figure 5 provides the timing for the synchronous ac tive pull-up and open-drain output signals. figure 5. synchronous active pullup and open-drain outputs signals timing clkout output signals output signals output signals b8 b7 b9 b8a b9 b7a b8b b7b clkout ts , bb ta , bi tea b13 b12 b11 b11a b12a b13a b15 b14 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 21 bus signal timing figure 6 provides the timing for the synchronous input signals. figure 6. synchronous input signals timing figure 7 provides normal case timing for input data. figure 7. input data timing in normal case clkout ta , bi tea , kr , retry bb , bg , br b16 b17 b16a b17a b16b b17 clkout ta d[0:31], dp[0:3] b16 b17 b19 b18 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 22 freescale semiconductor bus signal timing figure 8 provides the timing for the input data cont rolled by the upm in the memory controller. figure 8. input data timing when controlled by upm in the memory controller figure 9 through figure 12 provide the timing for the external bus read controlled by various gpcm factors. figure 9. external bus read timing (gpcm controlled?acs = 00) clkout ta d[0:31], dp[0:3] b20 b21 clkout a[6:31] csx oe we [0:3] ts d[0:31], dp[0:3] b11 b12 b23 b8 b22 b26 b19 b18 b25 b28 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 23 bus signal timing figure 10. external bus read timing (gpcm controlled?trlx = 0, acs = 10) figure 11. external bus read timing (gpcm controlled?trlx = 0, acs = 11) clkout a[6:31] csx oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b23 b26 b19 b18 b25 b24 clkout a[6:31] csx oe ts d[0:31], dp[0:3] b11 b12 b22b b8 b22c b23 b24a b25 b26 b19 b18 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 24 freescale semiconductor bus signal timing figure 12. external bus read timing (gpcm controlled?trlx = 1, acs = 10, acs = 11) clkout a[6:31] csx oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b27 b27a b22b b22c b19 b18 b26 b23 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 25 bus signal timing figure 13 through figure 15 provide the timing for the external bus write controlled by various gpcm factors. figure 13. external bus write timing (gpcm controlled?trlx = 0, csnt = 0) clkout a[6:31] csx we [0:3] oe ts d[0:31], dp[0:3] b11 b8 b22 b23 b12 b30 b28 b25 b26 b8 b9 b29a b29b mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 26 freescale semiconductor bus signal timing figure 14. external bus write timing (gpcm controlled?trlx = 0, csnt = 1) b23 b30a b30c clkout a[6:31] csx oe we [0:3] ts d[0:31], dp[0:3] b11 b8 b22 b12 b28b b28d b25 b26 b8 b28a b9 b28c b29c b29g b29a b29f mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 27 bus signal timing figure 15. external bus write timing (gpcm controlled?trlx = 1, csnt = 1) b23 b22 b8 b12 b11 clkout a[6:31] csx we [0:3] ts oe d[0:31], dp[0:3] b30d b30b b28b b28d b25 b29e b29i b26 b29d b28a b28c b9 b8 b29b mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 28 freescale semiconductor bus signal timing figure 16 provides the timing for the external bus controlled by the upm. figure 16. external bus timing (upm controlled signals) clkout csx b31d b8 b31 b34 b32b gpl_a [0?5], gpl_b [0?5] bs_a [0:3], bs_b [0:3] a[6:31] b31c b31b b34a b32 b32a b32d b34b b36 b35b b35a b35 b33 b32c b33a b31a mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 29 bus signal timing figure 17 provides the timing for the asynchronous asserted upwait signal controlled by the upm. figure 17. asynchronous upwait asserted detection in upm handled cycles timing figure 18 provides the timing for the asynchronous nega ted upwait signal controlled by the upm. figure 18. asynchronous upwait negated detection in upm handled cycles timing clkout csx upwait gpl_a [0?5], gpl_b [0?5] bs_a [0:3], bs_b [0:3] b37 b38 clkout csx upwait gpl_a [0?5], gpl_b [0?5] bs_a [0:3], bs_b [0:3] b37 b38 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 30 freescale semiconductor bus signal timing figure 19 provides the timing for the synchronous external master access controlled by the gpcm. figure 19. synchronous external master access timing (gpcm handled acs = 00) figure 20 provides the timing for the asynchronous external master memory access controlled by the gpcm. figure 20. asynchronous external master memory access timing (gpcm controlled?acs = 00) figure 21 provides the timing for the asynchronous exte rnal master control signals negation. figure 21. asynchronous external master?control signals negation timing clkout ts a[6:31], tsiz[0:1], r/w , burst csx b41 b42 b40 b22 clkout as a[6:31], tsiz[0:1], r/w csx b39 b40 b22 as csx , we [0:3], oe , gplx , bs [0:3] b43 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 31 bus signal timing table 7 provides interrupt timing for the mpc850. figure 22 provides the interrupt detection timing for the external level-sensitive lines. figure 22. interrupt detection timing for external level sensitive lines figure 23 provides the interrupt detection timing for the external edge-sensitive lines. figure 23. interrupt detection timing for external edge sensitive lines table 7. interrupt timing num characteristic 1 1 the timings i39 and i40 describe the testing conditions under which the irq lines are tested when being defined as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. the timings i41, i42, and i43 are specified to allow the correct function of the irq lines detection circuitry, and has no direct relation with the total system interrupt latency that the mpc850 is able to support 50 mhz 66mhz 80 mhz unit min max min max min max i39 irqx valid to clkout rising edge (set up time) 6.00 ? 6.00 ? 6.00 ? ns i40 irqx hold time after clkout. 2.00 ? 2.00 ? 2.00 ? ns i41 irqx pulse width low 3.00 ? 3.00 ? 3.00 ? ns i42 irqx pulse width high 3.00 ? 3.00 ? 3.00 ? ns i43 irqx edge-to-edge time 80.00 ? 121.0 ? 100.0 ? ns clkout irqx i39 i40 clkout irqx i39 i41 i42 i43 i43 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 32 freescale semiconductor bus signal timing table 8 shows the pcmcia timing for the mpc850. table 8. pcmcia timing num characteristic 50mhz 66mhz 80 mhz ffactor unit min max min max min max p44 a[6?31], reg valid to pcmcia strobe asserted. 1 1 psst = 1. otherwise add psst times cycle time. psht = 0. otherwise add psht times cycle time. these synchronous timings define when the wait_b signal is detected in order to freeze (or relieve) the pcmcia current cycle. the wait_b assertion will be effective only if it is detected 2 cycles before the psl timer expiration. see pcmcia interface in the mpc850 powerquicc user?s manual. 13.00 ? 21.00 ? 17.00 ? 0.750 ns p45 a[6?31], reg valid to ale negation. 1 18.00 ? 28.00 ? 23.00 ? 1.000 ns p46 clkout to reg valid 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns p47 clkout to reg invalid. 6.00 ? 9.00 ? 7.00 ? 0.250 ns p48 clkout to ce1 , ce2 asserted. 5.00 13.00 8.00 16.00 6.00 14.00 0.250 p49 clkout to ce1 , ce2 negated. 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns p50 clkout to pcoe , iord , pcwe , iowr assert time. ? 11.00 ? 11.00 ? 11.00 ? ns p51 clkout to pcoe , iord , pcwe , iowr negate time. 2.00 11.00 2.00 11.00 2.00 11.00 ? ns p52 clkout to ale assert time 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns p53 clkout to ale negate time ? 13.00 ? 16.00 ? 14.00 0.250 ns p54 pcwe , iowr negated to d[0?31] invalid. 1 3.00 ? 6.00 ? 4.00 ? 0.250 ns p55 wait_b valid to clkout rising edge. 1 8.00 ? 8.00 ? 8.00 ? ? ns p56 clkout rising edge to wait_b invalid. 1 2.00 ? 2.00 ? 2.00 ? ? ns mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 33 bus signal timing figure 24 provides the pcmcia access cycle timing for the external bus read. figure 24. pcmcia access cycles timing external bus read clkout a[6:31] reg ce1/ce2 pcoe , iord ts d[0:31] ale b19 b18 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 34 freescale semiconductor bus signal timing figure 25 provides the pcmcia access cycle timing for the external bus write. figure 25. pcmcia access cycles timing external bus write figure 26 provides the pcmcia wait signals detection timing. figure 26. pcmcia wait signal detection timing clkout a[6:31] reg ce1/ce2 pcwe , iowr ts d[0:31] ale b9 b8 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 p54 clkout wait_b p55 p56 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 35 bus signal timing table 9 shows the pcmcia port timing for the mpc850. figure 27 provides the pcmcia output port timing for the mpc850. figure 27. pcmcia output port timing figure 28 provides the pcmcia output port timing for the mpc850. figure 28. pcmcia input port timing table 9. pcmcia port timing num characteristic 50 mhz 66 mhz 80 mhz unit min max min max min max p57 clkout to opx valid ? 19.00 ? 19.00 ? 19.00 ns p58 hreset negated to opx drive 1 1 op2 and op3 only. 18.00 ? 26.00 ? 22.00 ? ns p59 ip_xx valid to clkout rising edge 5.00 ? 5.00 ? 5.00 ? ns p60 clkout rising edge to ip_xx invalid 1.00 ? 1.00 ? 1.00 ? ns clkout hreset output signals op2, op3 p57 p58 clkout input signals p59 p60 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 36 freescale semiconductor bus signal timing table 10 shows the debug port timing for the mpc850. figure 29 provides the input timing for the debug port clock. figure 29. debug port clock input timing figure 30 provides the timing for the debug port. figure 30. debug port timings table 10. debug port timing num characteristic 50 mhz 66 mhz 80 mhz unit min max min max min max d61 dsck cycle time 60.00 ? 91.00 ? 75.00 ? ns d62 dsck clock pulse width 25.00 ? 38.00 ? 31.00 ? ns d63 dsck rise and fall times 0.00 3.00 0.00 3.00 0.00 3.00 ns d64 dsdi input data setup time 8.00 ? 8.00 ? 8.00 ? ns d65 dsdi data hold time 5.00 ? 5.00 ? 5.00 ? ns d66 dsck low to dsdo data valid 0.00 15.00 0.00 15.00 0.00 15.00 ns d67 dsck low to dsdo invalid 0.00 2.00 0.00 2.00 0.00 2.00 ns dsck d61 d63 d62 d62 d63 dsck dsdi dsdo d64 d65 d66 d67 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 37 bus signal timing table 11 shows the reset timing for the mpc850. table 11. reset timing num characteristic 50 mhz 66mhz 80 mhz ffactor unit minmaxminmaxminmax r69 clkout to hreset high impedance ? 20.00 ? 20.00 ? 20.00 ? ns r70 clkout to sreset high impedance ? 20.00 ? 20.00 ? 20.00 ? ns r71 rstconf pulse width 340.00 ? 515.00 ? 425.00 ? 17.000 ns r72 ?????? ? r73 configuration data to hreset rising edge set up time 350.00 ? 505.00 ? 425.00 ? 15.000 ns r74 configuration data to rstconf rising edge set up time 350.00 ? 350.00 ? 350.00 ? ? ns r75 configuration data hold time after rstconf negation 0.00 ? 0.00 ? 0.00 ? ? ns r76 configuration data hold time after hreset negation 0.00 ? 0.00 ? 0.00 ? ? ns r77 hreset and rstconf asserted to data out drive ? 25.00 ? 25.00 ? 25.00 ? ns r78 rstconf negated to data out high impedance. ? 25.00 ? 25.00 ? 25.00 ? ns r79 clkout of last rising edge before chip tristates hreset to data out high impedance. ? 25.00 ? 25.00 ? 25.00 ? ns r80 dsdi, dsck set up 60.00 ? 90.00 ? 75.00 ? 3.000 ns r81 dsdi, dsck hold time 0.00 ? 0.00 ? 0.00 ? ? ns r82 sreset negated to clkout rising edge for dsdi and dsck sample 160.00 ? 242.00 ? 200.00 ? 8.000 ns mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 38 freescale semiconductor bus signal timing figure 31 shows the reset timing for the data bus configuration. figure 31. reset timing?configuration from data bus figure 32 provides the reset timing for the data bus weak drive dur ing configuration. figure 32. reset timing?data bus weak drive during configuration hreset rstconf d[0:31] (in) r71 r74 r73 r75 r76 clkout hreset d[0:31] (out) (weak) rstconf r69 r79 r77 r78 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 39 ieee 1149.1 electrical specifications figure 33 provides the reset timing for the debug port configuration. figure 33. reset timing?debug port configuration 7 ieee 1149.1 electrical specifications table 12 provides the jtag timings for the mpc850 as shown in figure 34 to figure 37 . table 12. jtag timing num characteristic 50 mhz 66mhz 80 mhz unit min max min max min max j82 tck cycle time 100.00 ? 100.00 ? 100.00 ? ns j83 tck clock pulse width measured at 1.5 v 40.00 ? 40.00 ? 40.00 ? ns j84 tck rise and fall times 0.00 10.00 0.00 10.00 0.00 10.00 ns j85 tms, tdi data setup time 5.00 ? 5.00 ? 5.00 ? ns j86 tms, tdi data hold time 25.00 ? 25.00 ? 25.00 ? ns j87 tck low to tdo data valid ? 27.00 ? 27.00 ? 27.00 ns j88 tck low to tdo data invalid 0.00 ? 0.00 ? 0.00 ? ns j89 tck low to tdo high impedance ? 20.00 ? 20.00 ? 20.00 ns j90 trst assert time 100.00 ? 100.00 ? 100.00 ? ns j91 trst setup time to tck low 40.00 ? 40.00 ? 40.00 ? ns j92 tck falling edge to output valid ? 50.00 ? 50.00 ? 50.00 ns j93 tck falling edge to output valid out of high impedance ? 50.00 ? 50.00 ? 50.00 ns j94 tck falling edge to output high impedance ? 50.00 ? 50.00 ? 50.00 ns j95 boundary scan input valid to tck rising edge 50.00 ? 50.00 ? 50.00 ? ns j96 tck rising edge to boundary scan input invalid 50.00 ? 50.00 ? 50.00 ? ns clkout sreset dsck, dsdi r70 r82 r80 r80 r81 r81 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 40 freescale semiconductor ieee 1149.1 electrical specifications figure 34. jtag test clock input timing figure 35. jtag test access port timing diagram figure 36. jtag trst timing diagram tck j82 j83 j82 j83 j84 j84 tck tms, tdi tdo j85 j86 j87 j88 j89 tck trst j91 j90 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 41 cpm electrical characteristics figure 37. boundary scan (jtag) timing diagram 8 cpm electrical characteristics this section provides the ac and dc electrical sp ecifications for the communi cations processor module (cpm) of the mpc850. 8.1 pio ac electrical specifications table 13 provides the parallel i/o timings for the mpc850 as shown in figure 38 . table 13. parallel i/o timing num characteristic all frequencies unit min max 29 data-in setup time to clock high 15 ? ns 30 data-in hold time from clock high 7.5 ? ns 31 clock low to data-out valid (cpu writes data, control, or direction) ? 25 ns tck output signals output signals input signals j92 j94 j93 j95 j96 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 42 freescale semiconductor cpm electrical characteristics figure 38. parallel i/o data-in/data-out timing diagram 8.2 idma controller ac electrical specifications table 14 provides the idma controller timings as shown in figure 39 to figure 42 . figure 39. idma external requests timing diagram table 14. idma controller timing num characteristic all frequencies unit min max 40 dreq setup time to clock high 7.00 ? ns 41 dreq hold time from clock high 3.00 ? ns 42 sdack assertion delay from clock high ? 12.00 ns 43 sdack negation delay from clock low ? 12.00 ns 44 sdack negation delay from ta low ? 20.00 ns 45 sdack negation delay from clock high ? 15.00 ns 46 ta assertion to falling edge of the clock setup time (applies to external ta )7.00 ? ns clkout data-in 29 31 30 data-out 41 40 dreq (input) clkout (output) mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 43 cpm electrical characteristics figure 40. sdack timing diagram?peripheral write, ta sampled low at the falling edge of the clock data 42 46 43 clkout (output) ts (output) r/w (output) ta (output) sdack mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 44 freescale semiconductor cpm electrical characteristics figure 41. sdack timing diagram?peripheral write, ta sampled high at the falling edge of the clock figure 42. sdack timing diagram?peripheral read data 42 44 clkout (output) ts (output) r/w (output) ta (output) sdack data 42 45 clkout (output) ts (output) r/w (output) ta (output) sdack mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 45 cpm electrical characteristics 8.3 baud rate generator ac electrical specifications table 15 provides the baud rate generator timings as shown in figure 43 . figure 43. baud rate generator timing diagram 8.4 timer ac electrical specifications table 16 provides the baud rate generator timings as shown in figure 44 . table 15. baud rate generator timing num characteristic all frequencies unit min max 50 brgo rise and fall time ? 10.00 ns 51 brgo duty cycle 40.00 60.00 % 52 brgo cycle 40.00 ? ns table 16. timer timing num characteristic all frequencies unit min max 61 tin/tgate rise and fall time 10.00 ? ns 62 tin/tgate low time 1.00 ? clk 63 tin/tgate high time 2.00 ? clk 64 tin/tgate cycle time 3.00 ? clk 65 clko high to tout valid 3.00 25.00 ns 52 50 51 brgo n 50 51 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 46 freescale semiconductor cpm electrical characteristics figure 44. cpm general-purpose timers timing diagram 8.5 serial interface ac electrical specifications table 17 provides the serial interface timings as shown in figure 45 to figure 49 . table 17. si timing num characteristic all frequencies unit min max 70 l1rclk, l1tclk frequency (dsc = 0) 1, 2 ? syncclk/2. 5 mhz 71 l1rclk, l1tclk width low (dsc = 0) 2 p + 10 ? ns 71a l1rclk, l1tclk width high (dsc = 0) 3 p + 10 ? ns 72 l1txd, l1st n , l1rq , l1xclko rise/fall time ? 15.00 ns 73 l1rsync, l1tsync valid to l1xclk edge edge (sync setup time) 20.00 ? ns 74 l1xclk edge to l1rsync, l1tsync, invalid (sync hold time) 35.00 ? ns 75 l1rsync, l1tsync rise/fall time ? 15.00 ns 76 l1rxd valid to l1xclk edge (l1rxd setup time) 17.00 ? ns 77 l1xclk edge to l1rxd invalid (l1rxd hold time) 13.00 ? ns 78 l1xclk edge to l1st n valid 4 10.00 45.00 ns 78a l1sync valid to l1st n valid 10.00 45.00 ns 79 l1xclk edge to l1st n invalid 10.00 45.00 ns 80 l1xclk edge to l1txd valid 10.00 55.00 ns 80a l1tsync valid to l1txd valid 4 10.00 55.00 ns 81 l1xclk edge to l1txd high impedance 0.00 42.00 ns clkout tin/tgate (input) tout (output) 64 65 61 62 63 61 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 47 cpm electrical characteristics figure 45. si receive timing diagram with normal clocking (dsc = 0) 82 l1rclk, l1tclk frequency (dsc =1) ? 16.00 or syncclk/2 mhz 83 l1rclk, l1tclk width low (dsc =1) p + 10 ? ns 83a l1rclk, l1tclk width high (dsc = 1) 3 p + 10 ? ns 84 l1clk edge to l1clko valid (dsc = 1) ? 30.00 ns 85 l1rq valid before falling edge of l1tsync 4 1.00 ? l1tclk 86 l1gr setup time 2 42.00 ? ns 87 l1gr hold time 42.00 ? ns 88 l1xclk edge to l1sync valid (fsd = 00) cnt = 0000, byt = 0, dsc = 0) ?0.00ns 1 the ratio syncclk/l1rclk must be greater than 2.5/1. 2 these specs are valid for idl mode only. 3 where p = 1/clkout. thus for a 25-mhz clko1 rate, p = 40 ns. 4 these strobes and txd on the first bit of the frame become valid after l1clk edge or l1sync, whichever is later. table 17. si timing (continued) num characteristic all frequencies unit min max l1rxd (input) 79 76 77 74 l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1st n (output) 71 70 rfsd=1 75 72 73 78 bit0 71a mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 48 freescale semiconductor cpm electrical characteristics figure 46. si receive timing with double-speed clocking (dsc = 1) l1rxd (input) l1rclk (fe=1, ce=1) (input) l1rclk (fe=0, ce=0) (input) l1rsync (input) l1st(4-1) (output) 72 rfsd=1 75 73 74 77 78 76 79 83a 82 l1clko (output) 84 bit0 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 49 cpm electrical characteristics figure 47. si transmit timing diagram l1txd (output) 79 81 80a l1tclk (fe=0, ce=0) (input) l1tclk (fe=1, ce=1) (input) l1tsync (input) l1st n (output) 70 tfsd=0 75 72 74 80 bit0 71 73 78 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 50 freescale semiconductor cpm electrical characteristics figure 48. si transmit timing with double speed clocking (dsc = 1) l1txd (output) l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 72 tfsd=0 75 73 74 78a 80 79 83a 82 l1clko (output) 84 bit0 78 81 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 51 cpm electrical characteristics figure 49. idl timing b17 b16 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b15 l1rxd (input) l1txd (output) l1st(4-1) (output) l1rq (output) 73 77 123456789 10 11 12 13 14 15 16 17 18 19 20 74 80 b17 b16 b15 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m 71 71 l1gr (input) 78 85 72 76 87 86 l1rsync (input) l1rclk (input) 81 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 52 freescale semiconductor cpm electrical characteristics 8.6 scc in nmsi mode electrical specifications table 18 provides the nmsi external clock timing. table 19 provides the nmsi internal clock timing. table 18. nmsi external clock timing num characteristic all frequencies unit min max 100 rclkx and tclkx frequency 1 (x = 2, 3 for all specs in this table) 1 the ratios syncclk/rclkx and syncclk/tclkx must be greater than or equal to 2.25/1. 1/syncclk ? ns 101 rclkx and tclkx width low 1/syncclk +5 ? ns 102 rclkx and tclkx rise/fall time ? 15.00 ns 103 txdx active delay (from tclkx falling edge) 0.00 50.00 ns 104 rtsx active/inactive delay (from tclkx falling edge) 0.00 50.00 ns 105 ctsx setup time to tclkx rising edge 5.00 ? ns 106 rxdx setup time to rclkx rising edge 5.00 ? ns 107 rxdx hold time from rclkx rising edge 2 2 also applies to cd and cts hold time when they are used as an external sync signal. 5.00 ? ns 108 cdx setup time to rclkx rising edge 5.00 ? ns table 19. nmsi internal clock timing num characteristic all frequencies unit min max 100 rclkx and tclkx frequency 1 (x = 2, 3 for all specs in this table) 1 the ratios syncclk/rclkx and syncclk/tclk1x must be greater or equal to 3/1. 0.00 syncclk/3 mhz 102 rclkx and tclkx rise/fall time ? ? ns 103 txdx active delay (from tclkx falling edge) 0.00 30.00 ns 104 rtsx active/inactive delay (from tclkx falling edge) 0.00 30.00 ns 105 ctsx setup time to tclkx rising edge 40.00 ? ns 106 rxdx setup time to rclkx rising edge 40.00 ? ns 107 rxdx hold time from rclkx rising edge 2 2 also applies to cd and cts hold time when they are used as an external sync signals. 0.00 ? ns 108 cdx setup time to rclkx rising edge 40.00 ? ns mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 53 cpm electrical characteristics figure 50 through figure 52 show the nmsi timings. figure 50. scc nmsi receive timing diagram figure 51. scc nmsi transmit timing diagram rclkx cdx (input) 102 100 107 108 107 rxdx (input) cdx (sync input) 102 101 106 tclkx ctsx (input) 102 100 104 107 txdx (output) ctsx (sync input) 102 101 rtsx (output) 105 103 104 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 54 freescale semiconductor cpm electrical characteristics figure 52. hdlc bus timing diagram 8.7 ethernet electrical specifications table 20 provides the ethernet timings as shown in figure 53 to figure 55 . table 20. ethernet timing num characteristic all frequencies unit min max 120 clsn width high 40.00 ? ns 121 rclkx rise/fall time (x = 2, 3 for all specs in this table) ? 15.00 ns 122 rclkx width low 40.00 ? ns 123 rclkx clock period 1 80.00 120.00 ns 124 rxdx setup time 20.00 ? ns 125 rxdx hold time 5.00 ? ns 126 rena active delay (from rclkx rising edge of the last data bit) 10.00 ? ns 127 rena width low 100.00 ? ns 128 tclkx rise/fall time ? 15.00 ns 129 tclkx width low 40.00 ? ns 130 tclkx clock period 1 99.00 101.00 ns 131 txdx active delay (from tclkx rising edge) 10.00 50.00 ns 132 txdx inactive delay (from tclkx rising edge) 10.00 50.00 ns 133 tena active delay (from tclkx rising edge) 10.00 50.00 ns tclkx ctsx (echo input) 102 100 104 txdx (output) 102 101 rtsx (output) 103 104 107 105 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 55 cpm electrical characteristics figure 53. ethernet collision timing diagram figure 54. ethernet receive timing diagram 134 tena inactive delay (from tclkx rising edge) 10.00 50.00 ns 138 clkout low to sdack asserted 2 ? 20.00 ns 139 clkout low to sdack negated 2 ? 20.00 ns 1 the ratios syncclk/rclkx and syncclk/tclkx must be greater or equal to 2/1. 2 sdack is asserted whenever the sdma writes the incoming frame destination address into memory. table 20. ethernet timing (continued) num characteristic all frequencies unit min max clsn(ctsx ) 120 (input) rclkx 121 rxdx (input) 121 rena(cdx ) (input) 125 124 123 127 126 last bit 122 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 56 freescale semiconductor cpm electrical characteristics figure 55. ethernet transmit timing diagram 8.8 smc transparent ac electrical specifications figure 21 provides the smc transparent timings as shown in figure 56 . table 21. serial management controller timing num characteristic all frequencies unit min max 150 smclkx clock period 1 1 the ratio syncclk/smclkx must be greater or equal to 2/1. 100.00 ? ns 151 smclkx width low 50.00 ? ns 151a smclkx width high 50.00 ? ns 152 smclkx rise/fall time ? 15.00 ns 153 smtxdx active delay (from smclkx falling edge) 10.00 50.00 ns 154 smrxdx/smsynx setup time 20.00 ? ns 155 smrxdx/smsynx hold time 5.00 ? ns tclkx 128 txdx (output) 128 tena(rtsx ) (input) notes: transmit clock invert (tci) bit in gsmr is set. if rena is deasserted before tena, or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. rena(cdx ) (input) 133 134 132 131 130 129 (note 2) mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 57 cpm electrical characteristics figure 56. smc transparent timing diagram 8.9 spi master ac electrical specifications table 22 provides the spi master timings as shown in figure 57 and figure 58 . table 22. spi master timing num characteristic all frequencies unit min max 160 master cycle time 4 1024 t cyc 161 master clock (sck) high or low time 2 512 t cyc 162 master data setup time (inputs) 50.00 ? ns 163 master data hold time (inputs) 0.00 ? ns 164 master data valid (after sck edge) ? 20.00 ns 165 master data hold time (outputs) 0.00 ? ns 166 rise time output ? 15.00 ns 167 fall time output ? 15.00 ns smclkx smrxdx (input) 152 150 smtxdx (output) 152 151 151a 154 153 155 154 155 note note: this delay is equal to an integer number of character-length clocks. 1. smsynx mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 58 freescale semiconductor cpm electrical characteristics figure 57. spi master (cp = 0) timing diagram figure 58. spi master (cp = 1) timing diagram spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) 162 data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 162 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 59 cpm electrical characteristics 8.10 spi slave ac electrical specifications table 23 provides the spi slave timings as shown in figure 59 and figure 60 . table 23. spi slave timing num characteristic all frequencies unit min max 170 slave cycle time 2 ? t cyc 171 slave enable lead time 15.00 ? ns 172 slave enable lag time 15.00 ? ns 173 slave clock (spiclk) high or low time 1 ? t cyc 174 slave sequential transfer delay (does not require deselect) 1 ? t cyc 175 slave data setup time (inputs) 20.00 ? ns 176 slave data hold time (inputs) 20.00 ? ns 177 slave access time ? 50.00 ns 178 slave spi miso disable time ? 50.00 ns 179 slave data valid (after spiclk edge) ? 50.00 ns 180 slave data hold time (outputs) 0.00 ? ns 181 rise time (input) ? 15.00 ns 182 fall time (input) ? 15.00 ns mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 60 freescale semiconductor cpm electrical characteristics figure 59. spi slave (cp = 0) timing diagram spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 173 173 170 msb lsb msb 181 177 182 175 179 spisel (input) 171 172 174 data msb lsb msb undef 181 178 176 182 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 61 cpm electrical characteristics figure 60. spi slave (cp = 1) timing diagram 8.11 i 2 c ac electrical specifications table 24 provides the i 2 c (scl < 100 khz) timings. ta ble 2 4. i 2 c timing (scl < 100 kh z ) num characteristic all frequencies unit min max 200 scl clock frequency (slave) 0.00 100.00 khz 200 scl clock frequency (master) 1 1.50 100.00 khz 202 bus free time between transmissions 4.70 ? s 203 low period of scl 4.70 ? s 204 high period of scl 4.00 ? s 205 start condition setup time 4.70 ? s 206 start condition hold time 4.00 ? s 207 data hold time 0.00 ? s 208 data setup time 250.00 ? ns 209 sdl/scl rise time ? 1.00 s spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 msb lsb 181 177 182 175 179 spisel (input) 174 data msb lsb undef 178 176 182 msb msb 172 173 173 171 170 181 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 62 freescale semiconductor cpm electrical characteristics table 25 provides the i 2 c (scl > 100 khz) timings. figure 61 shows the i 2 c bus timing. figure 61. i 2 c bus timing diagram 210 sdl/scl fall time ? 300.00 ns 211 stop condition setup time 4.70 ? s 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) * pre_scaler * 2). the ratio syncclk/(brgclk/pre_scaler) must be greater or equal to 4/1. ta ble 2 5. i 2 c timing (scl > 100 kh z ) num characteristic expression all frequencies unit min max 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) 1 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) * pre_scaler * 2). the ratio syncclk/(brg_clk/pre_scaler) must be greater or equal to 4/1. fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions 1/(2.2 * fscl) ? s 203 low period of scl 1/(2.2 * fscl) ? s 204 high period of scl 1/(2.2 * fscl) ? s 205 start condition setup time 1/(2.2 * fscl) ? s 206 start condition hold time 1/(2.2 * fscl) ? s 207 data hold time 0 ? s 208 data setup time 1/(40 * fscl) ? s 209 sdl/scl rise time ? 1/(10 * fscl) s 210 sdl/scl fall time ? 1/(33 * fscl) s 211 stop condition setup time 1/2(2.2 * fscl) ? s table 24. i 2 c timing (scl < 100 kh z ) ( continued ) num characteristic all frequencies unit min max scl 202 205 203 207 204 208 206 209 211 210 sda mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 63 mechanical data and ordering information 9 mechanical data and ordering information table 26 provides information on the mpc850 derivative devices. table 27 identifies the packages and operating frequencies available for the mpc850. 9.1 pin assignments and mechanical dimensions of the pbga the original pin numbering of the mpc850 conformed to a freescale proprieta ry pin numbering scheme that has since been replaced by the jedec pin numbering standard for this package type. to support table 26. mpc850 family derivatives device ethernet support number of sccs 1 1 serial communication controller (scc) 32-channel hdlc support 64-channel hdlc support 2 2 50 mhz version supports 64 time slots on a time division multiplexed line using one scc mpc850 n/a one n/a n/a mpc850de yes two n/a n/a mpc850sr yes two n/a yes mpc850dsl yes two no no table 27. mpc850 package/frequency/availability package type frequency (mhz) temperature (tj) order number 256-lead plastic ball grid array (zt suffix) 50 0c to 95c xpc850zt50bu xpc850dezt50bu xpc850srzt50bu xpc850dslzt50bu 66 0c to 95c xpc850zt66bu xpc850dezt66bu xpc850srzt66bu 80 0c to 95c xpc850zt80bu xpc850dezt80bu xpc850srzt80bu 256-lead plastic ball grid array (czt suffix) 50 -40c to 95c xpc850czt50bu xpc850deczt50bu xpc850srczt50bu xpc850dslczt50bu 66 XPC850CZT66BU xpc850deczt66bu xpc850srczt66bu 80 xpc850czt80b xpc850deczt80b xpc850srczt80b mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 64 freescale semiconductor mechanical data and ordering information customers that are currently using the non-jedec pin numbering scheme, two sets of pinouts, jedec and non-jedec, are presented in this document. figure 62 shows the non-jedec pinout of the pbga package as viewed from the top surface. figure 62. pin assignments for the pbga (top view)?non-jedec standard pc14 pb28 pb27 pc12 tck pb24 pb23 pa8 pa7 vddl pa5 pc7 pc4 pd14 pd10 pd8 pc15 pa14 pa13 pa12 tms pb26 pa15 pb30 pb29 pc13 trst n/c pc10 pa6 pb18 pc5 pd13 pd9 pd4 pd5 a8 a7 pb31 tdo tdi pc11 pb22 pc9 pb25 pa9 pc8 a11 a9 a12 pb19 pa4 pb16 pd15 pd12 pd7 pd6 pb17 pc6 pd11 pd3 irq7 irq1 irq0 t r p n m a15 a14 a13 a27 a19 a16 vddl a20 a21 a29 a23 a25 a28 a30 a22 a31 tsiz0 a26 we1 tsiz1 we0 we2 gpla3 gpla1 gpla2 cs6 d8 d0 d4 d1 d9 d11 d2 d3 k j h l d16 d5 d19 vddl d21 d6 d29 d7 d30 clkout dp3 n/c gnd g f vddh e d cs4 cs7 cs2 xfc vddsyn bi n/c cs3 cs1 bdip burst ipb4 aleb irq4 modck2 hreset sreset poreset vsssyn1 vsssyn br bb irq6 ipb3 ipb0 vddl extclkextal xtal kapwr c b a ta 16 15 14 13 12 11 10 9 876 54321 a6 a10 a17 a24 a18 we3 gpla0 cs5 wr gplb4 cs0 ts irq2 ipb7 ipb2 modck1 texp dp1 dp2 gpla4 tea bg ipb5 ipb1 ipb6 rstconf wa itb dp0 gpla5 d12 d13 d23 d27 d17 d10 d15 d14 d22 d18 d25 d20 d28 d24 d26 d31 n/c n/c n/c n/c n/c n/c mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 65 mechanical data and ordering information figure 63 shows the jedec pinout of the pbga package as viewed from the top surface. figure 63. pin assignments for the pbga (top view)?jedec standard for more information on the printed circuit board layout of the pbga package, including thermal via design and suggested pad layout, please refer to an- 1231/d, plastic ball grid array application note available from your local freescale sales office. pc14 pb28 pb27 pc12 tck pb24 pb23 pa8 pa7 vddl pa5 pc7 pc4 pd14 pd10 pd8 pc15 pa14 pa13 pa12 tms pb26 pa15 pb30 pb29 pc13 trst n/c pc10 pa6 pb18 pc5 pd13 pd9 pd4 pd5 a8 a7 pb31 tdo tdi pc11 pb22 pc9 pb25 pa9 pc8 a11 a9 a12 pb19 pa4 pb16 pd15 pd12 pd7 pd6 pb17 pc6 pd11 pd3 irq7 irq1 irq0 u t r p n a15 a14 a13 a27 a19 a16 vddl a20 a21 a29 a23 a25 a28 a30 a22 a31 tsiz0 a26 we1 tsiz1 we0 we2 gpla3 gpla1 gpla2 cs6 d8 d0 d4 d1 d9 d11 d2 d3 l k j m d16 d5 d19 vddl d21 d6 d29 d7 d30 clkout dp3 n/c gnd h g vddh f e cs4 cs7 cs2 xfc vddsyn bi n/c cs3 cs1 bdip burst ipb4 aleb irq4 modck2 hreset sreset poreset vsssyn1 vsssyn br bb irq6 ipb3 ipb0 vddl extclkextal xtal kapwr d c b ta 17 16 15 14 13 12 11 10 987 65432 a6 a10 a17 a24 a18 we3 gpla0 cs5 wr gplb4 cs0 ts irq2 ipb7 ipb2 modck1 texp dp1 dp2 gpla4 tea bg ipb5 ipb1 ipb6 rstconf wa itb dp0 gpla5 d12 d13 d23 d27 d17 d10 d15 d14 d22 d18 d25 d20 d28 d24 d26 d31 n/c n/c n/c n/c n/c n/c mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 66 freescale semiconductor mechanical data and ordering information figure 64 shows the non-jedec package dimensions of the pbga. figure 64. package dimensions for the plastic ball grid array (pbga)?non-jedec standard t a b c d e f g h j k l m n p r 256x bottom view e 0.20 6 5 4 3 2 1 b 0.15 c d d2 e2 a b 0.30 c ab side view dim min max millimeters a 1.91 2.35 a1 0.50 0.70 a2 1.12 1.22 a3 0.29 0.43 b 0.60 0.90 d 23.00 bsc d1 19.05 ref d2 e 23.00 bsc e1 19.05 ref e2 19.00 20.00 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and the seating plane are 4x 7 8 9 10 11 12 13 14 15 m m top view (d1) 15x e 15x e (e1) 4x e/2 0.20 c 0.35 c a3 256x c a a1 a2 seating plane e 1.27 bsc 19.00 20.00 16 mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 67 mechanical data and ordering information figure 65 shows the jedec package dimensions of the pbga. figure 65. package dimensions for the plastic ball grid array (pbga)?jedec standard u b c d e f g h j k l m n p r t 256x bottom view e 0.20 7 6 5 4 3 2 b 0.15 c d d2 e2 a b 0.30 c ab side view dim min max millimeters a 1.91 2.35 a1 0.50 0.70 a2 1.12 1.22 a3 0.29 0.43 b 0.60 0.90 d 23.00 bsc d1 19.05 ref d2 e 23.00 bsc e1 19.05 ref e2 19.00 20.00 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and the seating plane are 4x 8 9 10 11 12 13 14 15 16 m m top view (d1) 15x e 15x e (e1) 4x e/2 0.20 c 0.35 c a3 256x c a a1 a2 seating plane e 1.27 bsc 19.00 20.00 17 case 1130-01 issue b mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 68 freescale semiconductor document revision history 10 document revision history table 28 lists significant changes between revisions of this document. table 28. document revision history revision date change 2 7/2005 added footnote 3 to table 5 (previously table 4.5) and deleted iol limit. 1 10/2002 added mpc850dsl. corrected figure 25 on page 34. 0.2 04/2002 updated power numbers and added rev. c 0.1 11/2001 removed reference to 5 volt tolerance capability on peripheral interface pins. replaced si and idl timing diagrams with better images. updated to new template, added this revision table. mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 69 document revision history this page intentionally left blank mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 70 freescale semiconductor document revision history this page intentionally left blank mpc850 powerquicc? integrated communications processor hardware specifications, rev. 2 freescale semiconductor 71 document revision history this page intentionally left blank document number: mpc850ec rev. 2 07/2005 freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2005. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 2666 8080 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 (800) 441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com |
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